The present invention relates to a memory cell, and methods of forming same, where the memory cell includes a trench capacitor, an array FET, and a collar.
Memory arrays, such as dynamic random access memories (DRAMs), employ memory cell structures, where each memory cell stores one bit of information. A typical storage cell includes a single array transistor, e.g., a field effect transistor (FET), and a capacitor coupled from one of the source and drain of the FET to ground. The gate of the FET is connected to a word line and the other of the drain and source of the FET is connected to a bit line.
While the physical layout of a conventional memory cell may take on many forms, a popular configuration includes a trench capacitor and vertically aligned FET. An example of such a conventional structure of a memory cell 10 is illustrated in FIG. 1. The memory cell 10 includes a trench capacitor 14 and a vertically aligned FET 16. The trench capacitor 14 includes a polysilicon layer 18 and a buried plate 20 at a lower portion of the layer 18. The FET 16 includes a gate portion 22, a source portion 24, a drain portion 26, and a channel 28. The drain portion 26 may include a buried strap coupled to an upper portion of the polysilicon layer 18 of the trench capacitor 14. A collar 30 is disposed about the upper portion of the polysilicon layer 18.
Although the structure of the memory cell 10 of FIG. 1 is widely used in so-called trench capacitor design, it suffers from a significant disadvantage. In particular, a parasitic transistor is inherent in the memory cell 10 between the buried strap 26 and the buried plate 20. This parasitic transistor permits a significant electric field between the buried strap 26 and the buried plate 20, which also permits undesirable leakage along the trench from the buried plate 20 to the buried strap 26. Unfortunately, this undesirably affects the storage capabilities of the memory cell 10, including significantly reducing any charge stored on the trench capacitor 14.
Accordingly, there are needs in the art for new memory cell configurations, and methods of making same, which significantly reduce or eliminate the parasitic transistor between a buried strap and a buried plate in a trench capacitor storage cell, thereby significantly reducing any leakage between the buried plate and the buried strap.
In accordance with one or more aspects of the present invention, a memory cell includes a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.
Preferably, the re-entrant bend of the collar includes a substantially sharp distal edge. Further, it is preferred that the re-entrant bend of the collar is between about 200-300 nm in length. The collar is preferably formed of an oxide.
It is noted that the array FET may be vertically oriented or horizontally oriented.
In accordance with one or more further aspects of the present invention, a method of forming a memory cell includes etching a trench having an upper portion and a lower portion into a substrate; diffusing a dopant into the substrate proximate to the lower portion of the trench to form a buried plate; etching the trench in an area substantially at an upper portion of the buried plate to form a re-entrant bend in a sidewall of the trench; and forming a collar on the sidewall of the trench that includes the re-entrant bend and at least a portion of the upper portion of the trench.
Preferably, step of forming the re-entrant bend includes using NH4OH/HF etching cycles such that oxide consumption is less than about 60 angstroms. Preferably, the re-entrant bend of the collar includes a substantially sharp distal edge.
The method may further include forming a sacrificial collar on the upper portion of the trench that extends down to a lower edge prior to forming the buried plate; forming an oxide in the trench after forming the buried plate that is proximate to the buried plate and extends up the trench to an upper edge; filling the trench with resist to a level below the upper edge of the oxide; and removing a portion of the oxide from the trench that extends from the resist to the upper edge to form an exposed portion of the sidewall of the trench.
It is preferred that the exposed portion of the sidewall is between about 200-300 nm in length. The sacrificial collar may be formed from one of nitride and a polysilicon. Preferably, the step of forming a re-entrant bend in the sidewall of the trench includes etching the trench in the exposed area of the sidewall between the oxide and the sacrificial collar.
The method may further include forming a trench capacitor by filling at least a portion of the trench with a silicon layer having an upper portion and a lower portion; and forming an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, wherein the buried strap is in communication with the upper portion of the trench silicon layer and the collar is between the buried strap and the buried plate such that the re-entrant bend thereof is operable to decrease an electric field between the buried strap and the buried plate. The silicon layer of the trench capacitor may be formed of polysilicon.
In accordance with one or more further aspects of the present invention, a method of forming a memory cell includes etching a trench having an upper portion and a lower portion into a substrate; forming a sacrificial collar on the upper portion of the trench that extends down to a lower edge; diffusing a dopant into the substrate proximate to the lower portion of the trench to form a buried plate; forming an oxide in the trench that is proximate to the buried plate and extends up the trench to an upper edge; filling the trench with resist to a level below the upper edge of the oxide; removing a portion of the oxide from the trench that extends from the resist to the upper edge; removing the resist from the trench; etching the trench in the area between the lower edge of the sacrificial collar and the oxide to form a re-entrant bend in a sidewall of the trench; forming a collar on the sidewall of the trench that includes the re-entrant bend and at least a portion of the upper portion of the trench; filling at least a portion of the trench with a silicon layer having an upper portion and a lower portion; and forming an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, wherein the buried strap is in communication with the upper portion of the trench silicon layer and the collar is between the buried strap and the buried plate such that the re-entrant bend thereof is operable to decrease an electric field between the buried strap and the buried plate.
Other aspects, features, advantages, etc. will become apparent to one skilled in the art in view of the description herein taken in conjunction with the accompanying drawings.